Processors used in computing systems, for example internet services, operate on data very quickly and need a constant supply of data to operate efficiently. If a processor needs to obtain data from memory that is not in the processor's internal cache, it could result in may idle processor clock cycles while the data is being retrieved. Some prior art caching schemes that try to improve processor efficiency involve pushing data into a cache as soon as it is written into memory. One problem with these prior art schemes is that if the data is not needed until some time later, it may be overwritten and would need to be fetched from memory again thereby wasting interconnect bandwidth. Another problem with these prior art schemes is that in a multiprocessor system it would not always be possible to determine which processor will need the data.